Many CIMs present “leading process node,” “design win momentum,” or “capacity advantage” without proving yield maturity on the current node, capex-to-depreciation conversion, customer concentration in a handful of design wins, or export-control exposure on entire revenue lines. Semiconductor and chip due diligence (also called chipmaker, foundry, fabless, fab, integrated circuit, or microchip diligence) underwrites how the company converts capex into wafers, wafers into qualified parts, and parts into durable design wins. It tests process node yield and ramp position, fab capacity utilization and expansion economics, foundry vs fabless vs IDM margin structure, equipment depreciation cliffs, materials and geographic supply concentration (ASML EUV, substrates, Taiwan/Korea), customer concentration and design-in lock-in cycles, export controls and geopolitical revenue at risk, and whether the IP and roadmap survive node migration. It is not the same as manufacturing diligence (generic plant OEE), technology diligence (product stack), IP diligence (patents alone), customer concentration diligence (generic end-customer), or supply-chain diligence (generic suppliers). Semiconductor diligence underwrites whether the fab and design engine produces durable, qualified, cash-converting revenue through the hold period.
Semiconductor vs manufacturing vs technology vs IP
| Workstream | Primary question | Typical output |
|---|---|---|
| Semiconductor / chip DD | Is the node mature, the fab utilized, the design wins durable, and the revenue export-control safe? | Yield map, capacity bridge, design-win pipeline, export-control exposure |
| Manufacturing / plant DD | Is OEE, capacity, and throughput sustainable? | OEE, capacity utilization, bottleneck map |
| Technology / product DD | Is the product architecture and stack sound? | Architecture review, tech debt, roadmap |
| IP diligence | Is the patent portfolio defensible and clean? | Patent landscape, freedom-to-operate, litigation |
| Supply-chain DD | Are suppliers diversified and resilient? | Supplier map, single-source risk, lead times |
Six pillars of semiconductor & chip diligence
1. Fab capacity, utilization & expansion economics
Fab capacity in wafer starts per month (WSPM) by node and geometry, capacity utilization rate by fab and node, wafer-pricing trend, expansion projects and timelines (greenfield vs brownfield), capacity reservation and prepayment economics, and the gap between nameplate and qualified capacity. A fab running at 60% utilization burns cash; one at 95% cannot meet demand growth. Test whether the growth case depends on capacity that is not yet qualified, whether expansion capex is funded, and whether capacity reservations from anchor customers are committed or cancellable. Connect to manufacturing diligence for OEE benchmarks and capex diligence for expansion analysis.
2. Process node maturity, yield & technology roadmap
Current process node(s) (e.g. 3nm, 5nm, 7nm, 28nm, mature nodes), yield curve position for each node (ramp, maturing, mature, declining), defect density trend, time-to-volume for new nodes, roadmap to next node and capital required, and yield sensitivity of gross margin. A node mid-ramp can destroy margin for 18-36 months before reaching production yield. Test whether revenue depends on a node that is mid-ramp, whether the roadmap to the next node is funded and on schedule, and whether yield assumptions in the model are realistic against industry benchmarks. Align with technology diligence for architecture and IP diligence for process patents.
3. Foundry vs fabless vs IDM economics & margin structure
Business model (pure-play foundry, fabless, IDM, or hybrid), gross margin structure by model (foundry 30-55%, fabless 50-75%, IDM 25-50%), wafer pricing vs cost per wafer, foundry relationship terms (TSMC, Samsung Foundry, UMC, GlobalFoundries), capacity allocation agreements, dual-sourcing strategy, and margin sensitivity to foundry pricing. Fabless margins depend on foundry wafer pricing they do not control; foundry margins depend on utilization they must fill. Test whether the margin profile matches the business model, whether foundry dependencies create single-point-of-failure risk, and whether the growth case assumes margins achievable only with a different model.
4. Design wins, customer concentration & design-in lock-in
Top-customer concentration (often 30-60%+ in semis), design win pipeline and qualification status, design-in cycle length (12-36 months), share-of-wallet at key accounts (hyperscalers, automotive OEMs, smartphone OEMs), switching costs for customers to re-qualify a competitor part, product life cycles, and revenue durability of qualified designs. The loss of a single design win or major customer can crater a quarter. Test whether revenue is concentrated in design wins that can be displaced, whether qualification timelines create lock-in or just a head start, and whether customer concentration is disclosed honestly. Connect to customer concentration diligence and commercial diligence.
5. Equipment capex, depreciation & supply concentration
Equipment capex per fab ($1-4B+ per line, $10-20B+ for leading-edge greenfield), depreciation schedule and cliff risk, ASML EUV and DUV scanner allocation and lead times (18-30 months), specialty materials (photoresist from Japan, substrates, gases), single-source equipment and materials risk, geographic concentration of supply (Taiwan 60%+ of foundry, Korea for memory), and contingency for Taiwan strait disruption. Capex cycles create depreciation cliffs that distort EBITDA; supply concentration creates systemic risk. Test whether the model captures the next depreciation cliff, whether equipment lead times threaten the expansion timeline, and whether supply concentration is priced into risk. Align with supply-chain diligence and financial diligence.
6. Export controls, geopolitical risk & regulatory exposure
US export controls (BIS Entity List, October 2022 advanced-computing and equipment rules, subsequent revisions), China revenue exposure and at-risk percentage, restricted-party screening (customers, end-users, distributors), CHIPS Act funding conditions and national-security guardrails (capacity location, stock buyback restrictions, technology sharing), Taiwan contingency and supply-chain disruption modeling, foreign direct product rule exposure, and end-use/end-user compliance program maturity. Export controls can cut off entire revenue lines overnight. Test how much revenue is geography-restricted, whether the compliance program screens effectively, and whether the deal thesis depends on markets that controls may close. Connect to regulatory diligence, CFIUS diligence, and compliance diligence.
DI20-WELCOME) — useful for node-yield questions, capacity and capex framing, design-win concentration flags, export-control red flags, open-question lists, and data-room prioritization, not a substitute for full fab audits, yield data reviews, technology roadmap assessments, or counsel-led export control compliance reviews.
Stage sequencing (screen to IC)
| Stage | Semiconductor focus | Deal-team action |
|---|---|---|
| Teaser / CIM | Process node, design wins, capacity story | Flag node maturity and customer concentration claims |
| Desk diligence | Yield curve position, utilization, top-customer share | Red/amber/green; design-win hotspot list |
| Deep diligence | Capex/depreciation bridge, export-control mapping, supply concentration | Capacity and yield bridge; geopolitical risk map |
| IC / model | Cases for yield delay, customer loss, control tightening | Base / upside / downside with node and control cliffs |
| Post-close | Capacity plan, customer diversification, compliance upgrade | 100-day semiconductor plan with named owners |
Red flags
| Signal | Severity | Why it matters |
|---|---|---|
| Revenue depends on a node that is mid-ramp (below production yield) | Deal-Killer | Margin destroyed for 18-36 months; model assumes mature-node margins |
| Single customer >40% of revenue on a design win that can be displaced | Deal-Killer | Revenue can crater if customer re-qualifies a competitor |
| Capex expansion unfunded or equipment lead times threaten the timeline | Deal-Killer | Growth capacity may not arrive; depreciation cliff hits without revenue |
| Material China revenue at risk under export controls with no mitigation | High | Entire revenue lines can be cut off by regulatory action |
| Single-source ASML EUV or specialty materials with no dual-sourcing | High | Production halt risk on equipment or materials disruption |
| Foundry-dependent fabless with no capacity allocation guarantee | High | Wafer supply can be cut or repriced by foundry |
| Roadmap to next node not funded or behind schedule | High | Node obsolescence erodes design wins over hold period |
| CHIPS Act funding conditions not assessed for capacity-location constraints | Watch | Subsidy clawback or capacity-restriction risk |
Cost & timeline (traditional vs first-pass)
| Approach | Typical cost | Timeline | Best use |
|---|---|---|---|
| Full semiconductor specialist module (fab, yield, design wins, export controls) | $50K–$250K+ | 4–12 weeks | Leading-edge fabs, IDM acquisitions, fabless with heavy concentration |
| Targeted yield + customer + export-control deep-dive | $25K–$100K | 3–8 weeks | Mature-node fabs, fabless with cleaner books |
| Public first-pass semiconductor pack | $49 | Minutes to hours | Triage before specialist spend / IC framing |
50-point semiconductor & chip diligence checklist
- Fab capacity (WSPM) by node and geometry
- Capacity utilization rate by fab and node
- Wafer pricing trend and cost per wafer by node
- Expansion projects (greenfield vs brownfield) and timelines
- Capacity reservation and prepayment economics from anchor customers
- Gap between nameplate and qualified (production-ready) capacity
- Current process node(s) and geometry (3nm, 5nm, 7nm, 28nm, mature)
- Yield curve position per node (ramp / maturing / mature / declining)
- Defect density trend and yield-to-margin sensitivity
- Time-to-volume for new nodes and historical ramp speed
- Roadmap to next node: funded, scheduled, capital required
- Yield assumptions in model vs industry benchmarks
- Business model: pure-play foundry, fabless, IDM, or hybrid
- Gross margin profile vs model (foundry 30-55%, fabless 50-75%, IDM 25-50%)
- Foundry relationship terms (TSMC, Samsung, UMC, GlobalFoundries)
- Capacity allocation agreements and dual-sourcing strategy
- Margin sensitivity to foundry wafer pricing changes
- Top-customer concentration (target <25% per account; flag >40%)
- Design win pipeline and qualification status by customer
- Design-in cycle length (12-36 months) and lock-in economics
- Share-of-wallet at key accounts (hyperscalers, auto OEMs, smartphone OEMs)
- Switching cost for customers to re-qualify a competitor part
- Product life cycles and revenue durability of qualified designs
- Equipment capex per fab line ($1-4B+) and total greenfield cost ($10-20B+)
- Depreciation schedule and next depreciation cliff
- ASML EUV/DUV scanner allocation, lead times (18-30 months), and alternatives
- Specialty materials: photoresist, substrates, gases — single-source risk
- Geographic concentration of supply (Taiwan 60%+ foundry, Korea memory)
- Taiwan strait disruption contingency and supply-chain resilience plan
- US export controls: BIS Entity List screening of customers and end-users
- October 2022 advanced-computing and equipment rules — revenue at risk
- China revenue exposure and at-risk percentage under current rules
- Restricted-party screening program maturity and audit history
- CHIPS Act funding: conditions, national-security guardrails, clawback risk
- Foreign direct product rule exposure for non-US manufactured items
- End-use / end-user compliance program and training
- IP portfolio: process, design, and packaging patents — strength and litigation
- Advanced packaging (chiplets, CoWoS, HBM integration) roadmap and capacity
- Technology licensing in/out and royalty economics
- R&D spend as % of revenue and node-migration cadence
- Competitive landscape by node and end-market
- Working capital seasonality and inventory cycle risk (semis are cyclical)
- Integration impact on fab utilization, customer relationships, and roadmap
- Synergy claims that ignore depreciation cliffs or node-migration cost
- Leverage model sensitivity to cyclical downturn or customer loss
- Counsel workstream for export control compliance and CHIPS Act review
- Alignment of growth thesis with realistic yield ramps and design-win cycles
- IC materials: node-yield and capacity cliff cases, export-control scenarios
- Post-close capacity plan, customer diversification, and compliance upgrade roadmap
How deal teams use a first-pass pack
Use a first-pass semiconductor pack to structure early questions, pressure-test CIM node and design-win language, build a customer-concentration and yield-position heat map, flag export-control and supply-concentration red flags, and prioritize data-room asks before specialist semiconductor advisors, fab operations consultants, and export-control counsel engage. Pair it with manufacturing, technology, IP, customer concentration, supply-chain, regulatory, CFIUS, and LBO workstreams. It is an input to IC framing — not a full fab audit, yield data review, technology roadmap assessment, or counsel-led export control compliance review.
Underwrite the fab and design engine before you underwrite the growth case
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Get a structured first-pass diligence pack — useful input for semiconductor thesis tests, node-yield and capacity questions, design-win concentration risk, export-control flags, and IC prep, not a full specialist semiconductor study.
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